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D139 — Custom rules keep the per-class cache unless it would judge them differently

Context

Doc 05 §27 said: "Disallow masks retain the per-class cache. Physical-hole rules do too when independent of NetName, NetClass and inDiffPair. Other custom rules, including unparseable conditions, require exact checks." Exact mode (use_cache = false) also turns off the cost-to-go fields, which need the cache, so the GPU sits idle.

WholeBoard writes JLCPCB's manufacturing limits into every board's .kicad_dru: track_width, hole_size, via_diameter, annular_width, hole_to_hole, hole_clearance, edge_clearance, silk_clearance, text_height and text_thickness, one hole_to_hole rule with A.Net != B.Net (not readable: Net is unknown), and until now a clearance rule on A.Type != 'Zone' && B.Type != 'Zone'. Any one of them put the router in exact mode. On a 240 x 140 mm four-layer PoE switch (1,194 connections) every variant logged fields 0 GPU + 0 CPU over a 7,200 s run.

The router reads the rule engine per point only for clearance (RuleEngine::clearance, in both the cached and the exact path), disallow and physical_hole_clearance. Hole and edge clearances come from the board minimums in both paths; sizes, silk, text, length and skew are not per-point checks. A rule that is not applied (unreadable condition) is skipped in both paths. So for every rule above, exact mode judged each point as the cache does, only slower.

Decision

  • needs_exact_ is set only by a valid clearance rule whose condition references NetName or inDiffPair (the cache's stand-in net would be judged for every net of its class), and by a valid physical_hole_clearance rule that references NetName, NetClass or inDiffPair (unchanged). NetClass in a clearance condition keeps the cache: the cache is per class.
  • Cached via codes probe a via (ItemKind::Via) in fixed_code(via_probe = true) and fixed_via_code, as via_state does, so a clearance rule on Type, Width or Position_X/Y gives the same answer cached and exact. Without custom rules the probe kind does not change clearance().
  • Unreadable rules are still warned by name and not applied (rule 6); they no longer change how the rest is checked.

Alternatives

  • Read A.Net. It makes WholeBoard's hole-to-hole rule valid for the DRC, but leaves every other rule forcing exact mode. Separate change.
  • Fold plain minimums into the cache's values. Not needed: the router does not read them per point at all.
  • Keep exact mode for Type conditions. Would keep WholeBoard boards exact; the via probe makes the cache agree.

Consequences

Measured on the PoE switch (placed board, 300 s, eight variants, bench/records/d139/): with WholeBoard's rules file and the old engine the variants routed 116, 116, 221, 116, 116, 1079, 116, 92 (no fields). With this change and the file without its clearance rule: 882, 1004, 1057, 994, 899, 1099, 1006, 570 (7,695 GPU fields). With the clearance rule kept, six variants still stall near 116: that rule lowers the clearance of non-zone pairs from the class's 0.15 mm to the 0.127 mm board minimum, and the variants slow down on it (open; WholeBoard no longer writes the rule). Quick tier: 30/30 boards byte-identical, gates pass (PCBench boards have no rules file). Doc 05 §27 changed.

Memory. Boards that were in exact mode now allocate the per-class caches: three board-sized arrays per (net class, track width) in each variant's router, about 120 MB per class on a 240 x 140 mm four-layer board at 0.1 mm. The PoE switch had 83 net classes (WholeBoard wrote one per impedance pair) and the eight variants reached 181 GB of 184 GB within 17 minutes of routing. WholeBoard now merges identical classes; the engine still has no bound on cache memory (open: share caches between classes with the same values, or size them to the routed windows).