D140 — Unfilled zones are filled for routing; the router keeps custom hole clearance

Context

A 1,194-connection, four-layer WholeBoard board (PoE switch, every part on F.Cu, GND and +54V zones on In1/In2 written without fills, JLCPCB rules) routed 1,184 connections in two hours. The user saw it use too few vias and layers. The routed board showed why: the zones had no fill, so the router routed GND and +54V as tracks (1,773 mm, part of it on the other net's plane layer) instead of dropping vias into the planes, and those wide tracks crowded the fine-pitch escapes where the open connections were. KiCad's DRC of the same board also found 14 hole_clearance errors: the router ignored the custom "Hole to copper" rule (0.254 mm). Doc 05 §54.

Decision

• Zones without a fill are filled in memory before routing and the run uses soft zones (plane targets, refill after routing). On by default; route --no-fill-planes turns it off. The written zones stay as they were.
• RuleEngine::router_hole_clearance(): the board minimum raised to every applied custom hole_clearance rule, used by every router check. Rules with a condition or layer are applied everywhere, with a warning.

Alternatives

• Ask for --soft-zones. It does not help alone: a zone with no fill has no area, so it is no plane target.
• Write the fills into the output. KiCad refills on its own; leaving the zones as written keeps rule 8.
• Per-pair hole clearance in the router. Exact for conditional rules, but every cache and margin in route::Obstacles assumes one value; the floor is exact for unconditional rules, which is the common case (JLCPCB).

Consequences

• Boards without unfilled zones or custom hole-clearance rules route as before (quick tier byte-identical, 30/30).
• Soft zones bring their costs: the refill and refill repair after routing take time on large boards.
• The full-board result on the switch board (one hour, same options) was not measured before this was shipped.
• Open: conditions using A.Net are not evaluated (JLCPCB's "Hole to hole").