D120 — Per-shape zero edge clearance as in KiCad 10.0.6

Decision

The engine's DRC takes a required copper-to-edge clearance of zero as KiCad 10.0.6 does, per shape: a straight track, a via and a circle, oval or round-rect pad violate only once they cross the outline's centre line (touching is allowed, no epsilon: 1 nm of crossing is flagged); a rect or trapezoid pad and an arc track violate already when they touch it; above zero a gap below the clearance minus 0.5 µm violates (measured on a straight track only). Frozen as 71 KiCad results in tests/integration/edge_touch (issue #42)

Alternatives

One rule for all shapes (touching flagged: the old behaviour, 3 false errors on four srj20 boards; crossing only: would miss a flush rect pad that KiCad flags); the epsilon at zero clearance (KiCad has none there: 1 nm of crossing is flagged); a tolerance of a few nm; treating zone fills and copper graphics by measurement now (not measured, they keep the touching rule)

Reason

Issue #42: the router puts tracks on lattice points, so a track edge on the centre line of an outline is common, and a session that verifies with the engine's DRC refused a legal route. KiCad's answer depends on the shape class it tests with (segment and circle strictly, polygon and arc inclusively), so the test is a table of measured counts, not a formula; rule_parity's style (frozen oracle, --rejudge to refresh) keeps it from drifting