wholeboard.impedance

Controlled-impedance traces: widths and gaps from JLCPCB's layer stack, and a length check after routing.

A design lists its controlled nets in "impedance": [{"nets": ["USB_DP", "USB_DN"], "ohms": 90, "kind": "diff", "max_skew_mm": 1.25}, {"nets": ["RF_ANT"], "ohms": 50, "kind": "single"}, {"nets": ["QSPI_SCLK", "QSPI_SD0"], "kind": "bus", "max_length_mm": 30, "max_match_mm": 5}]

An entry may name a routing profile ("profile": "usb2_hs") for an interface's limits; its own fields override the profile's. Limits: max_length_mm (each net), max_skew_mm (within a pair), max_match_mm (between the nets of a bus), max_vias (each net), max_stub_mm (a branch off the main run, e.g. to an ESD diode), and match with max_skew_between_mm (pairs that share a "match" name stay within that length of each other). Profiles: {PROFILES}. Building blocks carry the profile of the interfaces they provide, so the checks apply wherever they are used.

Widths use the IPC-2141 microstrip formulas for an outer-layer trace over the nearest plane. They are approximate (the coupled-pair formula most of all): order 4 and 6 layer boards with impedance control and the stack-up named here (free at JLCPCB), and check the figures in JLCPCB's impedance calculator.

profiled(group)

A group with its profile's limits filled in (the group's own fields win).

microstrip(w, h, er, t=COPPER_MM)

Single-ended impedance of an outer-layer trace (IPC-2141).

design_rule(group, layers, thickness, clearance)

Width (and gap) for one impedance group, and whether it is practical on this stack-up.

netclasses(spec)

Extra KiCad net classes for the controlled nets: (name, width, gap, nets).

check(spec, geo)

After routing: each controlled net's length and narrowest track, and each pair's skew.