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Mains requirements

Generated from the code

This page is written from wholeboard/mains.py each time the site is built. To change it, change the code.

An aid, not a certification

These checks cover spacing on the board, the fuse and the isolation barrier. Have a mains design reviewed, and build it into an enclosure that keeps fingers out.

Spacing for common voltages

Pollution degree 2, FR-4 (material group IIIb). Overvoltage category II is the default for plug-in equipment; set overvoltage_category: 3 for fixed wiring. Where the figures come from is on Standards and sources.

Working voltage Overvoltage category Peak (V) Impulse (V) Between mains nets, outer (mm) Between mains nets, inner (mm) Reinforced clearance (mm) Basic creepage (mm) Reinforced creepage (mm)
120 V II 170 1500 1.25 0.2 1.5 1.5 3.0
120 V III 170 2500 1.25 0.2 3.0 1.5 3.0
230 V II 325 2500 2.5 0.25 3.0 2.5 5.0
230 V III 325 4000 2.5 0.25 5.5 2.5 5.5
240 V II 339 2500 2.5 0.25 3.0 2.5 5.0
240 V III 339 4000 2.5 0.25 5.5 2.5 5.5
277 V II 392 2500 2.5 0.25 3.0 3.2 6.4
277 V III 392 4000 2.5 0.25 5.5 3.2 6.4
400 V II 566 4000 2.83 1.41 5.5 4.0 8.0
400 V III 566 6000 2.83 1.41 8.0 4.0 8.0

Slots cut to lengthen creepage are 1 mm wide. Measurements are compared with a tolerance of 0.01 mm.

How parts are recognised

WholeBoard matches these patterns (case-insensitive) against the part's value, part number, footprint and description (a fuse's reference counts too). "barrier" on a part overrides the match.

Isolation barrier

HLK-?PM|HLK-?\d|IRM-?\d|TRANSFORMER|PC8\d\d|LTV-?\d|EL3?8\d\d|TLP\d|6N13\d|H11\w|MOC30|FOD\w|ADUM|ISO7\d|ISO1\d|SI86|SI87|CA-IS|NSI\d|OPTO|RELAY|HF\d+F|SRD-|G5LE|G5V
(also any T or K reference, and any part with "barrier": true)

Fuse

FUSE|^F\d|MF-?R|PPTC|POLYFUSE

A net name that looks like mains

^(AC_?(L|N|LINE|LIVE|NEUTRAL|IN)\w*|LINE|LIVE|NEUTRAL|MAINS\w*|\d{3}V_?AC|VAC\w*)$

A part that suggests mains

HLK-?PM|IRM-?\d|VARISTOR|MOV|Fuseholder|Converter_ACDC|X2|275V|250VAC

KiCad rules written for a mains design

For a design with mains declared as {"nets": ["AC_L", "AC_N"], "volts": 230}, the .kicad_dru gets:

# Mains: 230 V working, see wholeboard/mains.py
(rule "Mains: functional spacing, outer layers"
  (layer outer)
  (condition "A.NetClass == 'Mains' && B.NetClass == 'Mains' && !(A.Type == 'Pad' && B.Type == 'Pad')")
  (constraint clearance (min 2.5mm)))
(rule "Mains: functional spacing, inner layers"
  (layer inner)
  (condition "A.NetClass == 'Mains' && B.NetClass == 'Mains' && !(A.Type == 'Pad' && B.Type == 'Pad')")
  (constraint clearance (min 0.25mm)))
(rule "Mains: reinforced isolation"
  (condition "(A.NetClass == 'Mains' || A.NetClass == 'Mains side') && B.NetClass != 'Mains' && B.NetClass != 'Mains side'")
  (constraint clearance (min 3mm))
  (constraint creepage (min 5mm)))
(rule "Mains: reinforced isolation, surface copper"
  (layer outer)
  (condition "(A.NetClass == 'Mains' || A.NetClass == 'Mains side') && B.NetClass != 'Mains' && B.NetClass != 'Mains side' && !(A.Type == 'Pad' && B.Type == 'Pad')")
  (constraint clearance (min 5mm)))

What the designer is told

Mains safety: creepage, clearance, a fuse and an isolation barrier for boards that touch mains.

A design that connects to mains declares it in "mains":
  {"nets": ["AC_L", "AC_N"], "volts": 230, "isolated": true}
volts is the working voltage (rms for AC; default 250, which covers 230 and 240 V mains). isolated true (the
default) means the low-voltage side is meant to be safe to touch (SELV): it must be separated from everything on
the mains side by reinforced insulation, through an isolation barrier part: an isolated supply module (HLK-PM01,
IRM-02), a transformer, an optocoupler or digital isolator, or a relay; mark any other part that crosses the
barrier (a Y capacitor) with "barrier": true. isolated false means the whole board is live (a capacitive dropper,
a non-isolated buck): it must never be touched while plugged in, and only the mains nets' own spacing is checked.
The mains side is every net reached from the mains nets through parts that are not barrier parts.

Requirements, for pollution degree 2 and FR-4 (material group IIIb), overvoltage category II (overvoltage_category
3 for fixed wiring):
  - between the listed mains nets (live and neutral, before and after the fuse, the rectified bus): IPC-2221 table
    6-1 B2 (outer layers) and B1 (inner) for the peak voltage (functional insulation). List every net that carries
    the full mains voltage; other mains-side nets (an LED feed, a controller's supply) are not held to it;
  - from the mains side to the low-voltage side, mounting holes and anything else: IEC 62368-1 / IEC 60664-1
    reinforced insulation: clearance for the next mains transient step up (3.0 mm at 230 V), creepage twice the
    basic value (5.0 mm at 250 V). Creepage runs along the board surface, so a milled slot (at least 1 mm wide)
    makes it longer: WholeBoard cuts one under each barrier part whose pins are closer than that, unless the part
    says "slot": false.
WholeBoard refuses to finish a mains design with no fuse on the mains input, no isolation barrier (when isolated)
or a spacing that fails, and says why. These checks are an aid, not a certification: have a mains design
reviewed, and build it into an enclosure that keeps fingers out.