wholeboard.mains

Mains safety: creepage, clearance, a fuse and an isolation barrier for boards that touch mains.

A design that connects to mains declares it in "mains": {"nets": ["AC_L", "AC_N"], "volts": 230, "isolated": true} volts is the working voltage (rms for AC; default 250, which covers 230 and 240 V mains). isolated true (the default) means the low-voltage side is meant to be safe to touch (SELV): it must be separated from everything on the mains side by reinforced insulation, through an isolation barrier part: an isolated supply module (HLK-PM01, IRM-02), a transformer, an optocoupler or digital isolator, or a relay; mark any other part that crosses the barrier (a Y capacitor) with "barrier": true. isolated false means the whole board is live (a capacitive dropper, a non-isolated buck): it must never be touched while plugged in, and only the mains nets' own spacing is checked. The mains side is every net reached from the mains nets through parts that are not barrier parts.

Requirements, for pollution degree 2 and FR-4 (material group IIIb), overvoltage category II (overvoltage_category 3 for fixed wiring): - between the listed mains nets (live and neutral, before and after the fuse, the rectified bus): IPC-2221 table 6-1 B2 (outer layers) and B1 (inner) for the peak voltage (functional insulation). List every net that carries the full mains voltage; other mains-side nets (an LED feed, a controller's supply) are not held to it; - from the mains side to the low-voltage side, mounting holes and anything else: IEC 62368-1 / IEC 60664-1 reinforced insulation: clearance for the next mains transient step up (3.0 mm at 230 V), creepage twice the basic value (5.0 mm at 250 V). Creepage runs along the board surface, so a milled slot (at least 1 mm wide) makes it longer: WholeBoard cuts one under each barrier part whose pins are closer than that, unless the part says "slot": false. WholeBoard refuses to finish a mains design with no fuse on the mains input, no isolation barrier (when isolated) or a spacing that fails, and says why. These checks are an aid, not a certification: have a mains design reviewed, and build it into an enclosure that keeps fingers out.

config(spec)

The design's mains settings, with nets of class "hv" added, or None if it has no mains.

sides(spec, cfg)

The mains-side nets (reached from the mains nets through non-barrier parts), and each barrier part's pins.

validate(spec)

Before building: refuse a mains design with no fuse or no isolation barrier.

items(geo)

Copper items: {net, layers, segs, r, box, what}.

cutouts(geo)

Holes and slots milled through the board: Edge.Cuts loops other than the outline, as polygons.

creepage(p, q, holes)

The shortest path from p to q along the board surface, around the slots.

check(spec, geo)

After routing: the closest approach between the mains side and everything else, against the requirements.

slots_for(spec, geo)

A milled slot under each barrier part whose mains and low-voltage pins are closer than the creepage needed: {ref, centre, length, angle, width} in board coordinates.

slot_outline(s)

Edge.Cuts lines and arcs for a slot with rounded ends.

add_slots(pcb, spec, geo)

Cut the slots into a placed board, before routing.

dru_rules(spec)

Custom rules for KiCad's DRC (and TraceMaker): functional spacing on the mains nets, reinforced clearance and creepage from the mains side to everything else.

netclasses(spec)

Mains net class names to their nets, for the project file.