wholeboard.pipeline

Turn a design spec into a checked, routed, quoted board, step by step.

check_parts(spec)

Stock and package sanity checks against JLCPCB's library (warnings only).

build(p, spec, view_origin=None, by='')

Build one revision of the board and record it in the revision history.

run_sim(p, spec, rdir)

Simulate the design with ngspice and show the results in the "sim" step.

sim_summary(res)

What the AI needs from a simulation: no waveforms.

run_enclosure(p, spec, enc, pcb=None)

Build the AI's enclosure design in FreeCAD around the finished board; returns a summary.

make_report(p)

The PDF project report, shown with the outputs.

run_case(p, spec, pcb=None)

Check the board fits the user's own box and draw the drilling templates.

run_panel(p, spec, nx, ny)

Draw the panel with KiKit and export its Gerbers, CPL and BOM, from the last finished board.

build_firmware(p)

Compile the latest revision's starter firmware with PlatformIO and offer the result for flashing.

refresh_bom(p, spec)

Rewrite the latest revision's BOM, CPL and project zip after part numbers change.

save_simlab_video(p, data, kind)

Keep a Sim Lab video recorded in the browser, as a constant-rate MP4 when ffmpeg is installed.